Category Archives: IP Cores

The FC-GPIO core has two clock domains. All registers are in system clock domain except RGPIO_IN that can be clocked by system or external clock reference.

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FMC-CANbus IP supports CAN 2.0 & CAN-FD (ISO 11898- 1.2015, plus earlier ISO and Bosch specifications) TTCAN (ISO 11898-4 level 1)

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The FC-A429 macro implements a ARINC 429 protocol with Transmit and Receive Controllers . It allows for the parallel-bus microprocessor communication.

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FC-1533 is Mil-Std-1553 IP for FPGAs and ASIC, suitable for any MIL-STD-1553 BC,RT,MT implementation. VHDL code is technology independent.

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FC300 is an FPGA IP core implementing the complete OFDM physical layer, based on 802.11a/g/n.

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