FMCP-DAC12p0 is a 4 channels DAC module based on the industry standard FMC+ standard. It utilizes 2 AD9172 on the board for Digital to Analog Conversion and interfaces works through JESD204B IP core.
This is an advanced High-speed Digital to Analog Convertor in the market with 16-bit resolution capable of a sample rate at 12.6 GSPS and has dual channels in a single package. Each DAC IC can be configured via SPI interface separately.
The module includes an HMC7044 – High performance 3.2GHz JESD204B jitter attenuator for obtaining best results. On board the module there is a 100 MHz onboard VCXO; and 10 MHz TCXO as reference clock, or external user reference clock;
To maximizing the utilization of FPGA carrier card transceivers FMCP-DAC12p0 has a carrier type FMC+ connector on the solder side. So an FMCP-ADC3p0 can be piggy backed by this module. This means that all 16 Rx and TX transceivers from the carrier card can be used. This is a major optimization of transceivers’ use offered by this module. on 1 FMC+ site a 4 channels DAC and a 4 channel ADC can coexist and provide major savings in space and resource use.
- Two AD9172 dual 16-bit 12GSPS Digital to Analog Converter, JESD204B based.
- HMC7044 – High performance 3.2GHz JESD204B jitter attenuator.
- Six connectors, SSMC type:
- Four connectors for DAC output signals
- One for reference clock
- One Trigger input
- JESD204B Subclass 1 capable;
- 100 MHz onboard VCXO;
- 10 MHz onboard TCXO as reference clock, or external user reference clock;
- Vadj supported voltages:1.8V, 2.5V, 3.3V;
- FMC+ connectors:
First connector – HPC FMC+ mezzanine connector (ASP-184330-01) will use LA banks for digital interface, 16 Ten-gigabit pairs will be used to transmit data from a carrier to DACs.
Second connector – HPC FMC+ carrier connector (ASP-184329-01) provide piggyback connectivity of FMCP_ADC3p0 board.
- Trigger input:
Trigger input allows user to synchronize various applications, or to start DAC output when trigger is fired.
- Input type: DC – coupled, single ended, 3.3V logic, ESD protected;
- Input impedance : >100 kOhm;
- Frequency range: DC – 10 MHz;
- Maximum input voltage – 3.3V;
- Logic “0” voltage <0.4V;
- Triggering voltage >1V.
- Defense and Aerospace
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
- Electronic test and measurement systems
- Phased array radar and electronic warfare
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
|rendered image component side||rendered image solder side||component side||FMCP-DAC12p0 component side showing piggy back FMC+ connector|
A complete Vivado project showing sample digital signals sent to DAC ICs by using the Xilinx JESD204B IP core is provided.