Ultrasound, PET and MRI produce very different signals. Can one four-channel acquisition module serve all three? Mostly yes. The ADCs are not the reason. The clock and the serial fabric are.
- The FMC-ADC500CD has four 16-bit, 1 GSPS ADC channels, four 16-bit DAC channels, an HMC7044 clock and eight JESD204B lanes on one HPC FMC card.
- Its sample rate and bit depth are well above what any of the three modalities strictly needs. With decimation, that extra rate turns into extra dynamic range.
- What really carries the design is deterministic, multi-channel timing: JESD204B Subclass 1 with a shared SYSREF.
- Its best fit is research platforms, prototypes and detector R&D. With four channels per card, it does not replace high-density ASICs in a 128-element or full-ring production system.
Every imaging group knows the pattern. A new modality comes along, and the team builds a new acquisition board for it. Ultrasound needs dozens of phase-coherent RF channels. PET needs timing to a fraction of a nanosecond. MRI needs very wide dynamic range at a few hundred MHz. Because the signals differ so much in rate, bandwidth and noise floor, the analog front end becomes the part teams are least willing to share. It is also the part that costs the most to redesign.
This article tests a different idea: one modular front end, reused across all three chains. For each modality, I look at what the signal actually demands and name the board feature that meets it. I also say plainly where the fit ends. The aim is to treat the front end as a reusable building block rather than a custom board for every program.
What’s on the board
Here are the parts of the FMC-ADC500CD, listed in the order the signal meets them:
- Four ADC channels from two dual-channel TI ADS54J60 converters. Each is 16-bit at up to 1 GSPS, with on-chip decimation for lower-bandwidth signals.
- Four single-ended 50 Ω inputs, 1.9 Vpp full scale and rated DC to 500 MHz. Firmware selects AC or DC coupling, so no jumpers are needed.
- Four DAC channels from a TI DAC39J84 (16-bit, up to 2.8 GSPS). The outputs cover 10 MHz to 1.25 GHz, so the DAC can synthesize IF or RF waveforms directly.
- An ADI HMC7044 clock generator with up to 14 outputs to 3.2 GHz, JESD204B SYSREF generation and about 44 fs RMS jitter (datasheet figure). On-board VCXO and TCXO references and an external clock input are also provided.
- Eight JESD204B lanes at up to 12 Gbps each over the HPC FMC connector, with Subclass 1 deterministic latency.
- An LVTTL 3.3 V trigger input that timestamps the ADC sample stream.
Two of these do most of the work. JESD204B replaces dozens of parallel LVDS pairs with eight serial lanes. That makes dense, multi-card carriers practical to route. SYSREF from the HMC7044 aligns every converter to the same sample instant with deterministic latency, so channel N on card A and channel M on card B agree on time. Beamforming, coincidence timing and phased-array MRI receive all depend on that alignment. The coupling switch and the trigger input then let you adapt the same hardware to each modality.
Ultrasound: digitizing the RF echo
An ultrasound probe fires a short burst a few cycles long, then listens for the echoes. Diagnostic center frequencies run from about 1 MHz to 18 MHz, and the echo comes back as RF at that frequency. The front end has to digitize it with enough fidelity and timing accuracy for the beamformer to apply fractional-sample delays across the whole aperture.
Each element’s receive chain is a low-noise amplifier, then a variable-gain amplifier for time-gain compensation, then an anti-aliasing filter, then the ADC. Dynamic range is the hard requirement. It runs from roughly 70 dB for B-mode imaging up to about 160 dBFS/Hz for continuous-wave Doppler. Linear arrays typically have 64 to 256 elements. One published single-FPGA beamformer digitizes 128 elements at 14 bits and 62.5 MSPS. That is 112 Gb/s of raw data before beamforming.
How the board maps. At 1 GSPS, a 1–18 MHz echo is heavily oversampled. That is a resource, not waste. Decimating from 1 GSPS down to about 62.5 MSPS is a 16× oversampling ratio, which gives up to about 12 dB of in-band processing gain (10·log₁₀16) on top of the converter’s native SNR. The sample rate is clearly not the constraint.
Coherence is what matters. Every card shares the same sample clock and SYSREF instant, so the beamformer’s delays line up across modules. The AC/DC coupling switch handles both DC-biased and AC-coupled probe interfaces. The DAC39J84 can generate arbitrary transmit waveforms, such as chirps, coded excitation and apodized bursts. These are useful for research into ultrafast and plane-wave imaging.
PET: timing at the picosecond level
In PET, a radionuclide emits a positron, which annihilates with an electron. The annihilation produces two 511 keV gamma photons travelling in nearly opposite directions. A pair counts as a true event only when both photons are detected within the coincidence window and both have the right energy.
Two time scales matter here, and they are often confused. The coincidence window is typically a few nanoseconds. The timing resolution, measured as coincidence time resolution (CTR), is far finer. Modern time-of-flight scanners achieve a few hundred picoseconds, and that resolution is what localizes the event along the line of response and improves image SNR. Each detector pairs a scintillator with a PMT or SiPM, and the signal splits into an energy path (pulse integral) and a timing path (leading edge).
How the board maps. Published designs typically call for 10–12-bit ADCs sampling well above 40 MSPS to capture the pulse leading edge. At 1 GSPS and 16 bits, the ADS54J60 samples every nanosecond. With digital constant-fraction discrimination or template fitting on the waveform, timing can be resolved well below the sample period. The same samples feed both the energy path and the timing path.
On the timing side, SYSREF aligns every channel to a common reference. That makes cross-card coincidence measurement practical. The external trigger timestamps the sample stream, and the DAC39J84 can inject calibration pulses for skew and gain correction across channels.
MRI: from Larmor frequency to k-space
MRI, like ultrasound, uses no ionizing radiation. Its receive coils pick up the small RF voltage induced by precessing nuclear spins. The carrier is the Larmor frequency, and it scales with field strength. For protons, the gyromagnetic ratio is 42.58 MHz/T, so the carrier is about 64 MHz at 1.5 T, 128 MHz at 3 T and 298 MHz at 7 T. The information bandwidth of a single readout is small, from a few kHz to a few hundred kHz.
Classic receivers are superheterodyne: they mix down to an IF before digitizing. Modern systems sample the RF directly at well over 100 MSPS with 16-bit converters, aiming for more than 100 dB of dynamic range. An ISMRM receiver tutorial puts numbers on it. A 14-bit ADC over a 10 MHz bandwidth delivers about 153 dB·Hz, while the full receive chain needs closer to 180. That gap is why automatic gain control and low clock jitter matter so much.
How the board maps. All three field strengths, 64, 128 and 298 MHz, sit in the first Nyquist zone of a 1 GSPS converter and inside the 500 MHz input range. The board can therefore sample directly from 1.5 T up to 7 T with no mixer stage. A digital down-converter and decimation in the FPGA then narrow the band to the readout bandwidth, and each halving of bandwidth adds about 3 dB of processing gain. The resulting complex baseband samples are what get assembled into k-space before reconstruction. Multi-channel receive arrays of 16 to 128 coils need per-coil digitization in parallel, which matches the multi-card, single-clock-tree topology. The DAC39J84 can act as a low-level RF exciter ahead of the RF power amplifier.
At a glance: what each modality needs
| Modality | Signal | What it needs | Board feature that carries it | Fit |
|---|---|---|---|---|
| Ultrasound | RF echo, 1–18 MHz | Phase-coherent multi-channel sampling, 70 dB+ dynamic range | Shared clock + SYSREF; decimation gain; DAC for transmit waveforms | Strong for research and prototyping |
| PET | Scintillator pulses, 511 keV | Sub-ns timing, energy integration | 1 GSPS waveform capture; SYSREF alignment; trigger timestamps; DAC calibration pulses | Strong for detector R&D |
| MRI | RF at 64–298 MHz (1.5–7 T) | Direct RF sampling, >100 dB dynamic range, many coils | 500 MHz input range; 16-bit depth; FPGA DDC; multi-card topology | Clean fit from 1.5 T to 7 T |
Choosing which modality to build for
Read the three sections together and a pattern appears. The converter specs are not what decides the fit. All three modalities sit comfortably inside the board’s rate and resolution. What decides it is multi-channel timing: getting every channel, on every card, to agree on when a sample was taken. That is exactly what the JESD204B fabric and SYSREF provide.
For ultrasound and PET, the board is a strong research and prototyping platform. For MRI it is a clean direct-sampling receiver from 1.5 T through 7 T. Across a product line, reusing one validated front end means one clock tree to characterize, one JESD link to bring up and one set of firmware IP to maintain. Those savings in design and verification grow with every program. Teams building on Sundance DSP carriers should also read Beyond the Bezel, which covers the FMC breakout and signal-integrity details.
- Sample rate is not the bottleneck in any of the three modalities. Use the extra rate, through decimation, to gain dynamic range.
- Deterministic timing (JESD204B Subclass 1 + SYSREF) is the feature that makes one front end reusable across modalities.
- Four channels per card makes this board a natural fit for research systems, prototypes and detector benches. For production channel counts, plan on dedicated AFEs or ASICs.
- Analog conditioning (LNAs, TGC, HV transmit, coil preamps) remains modality-specific. Budget for it from day one.
The bottom line
The FMC-ADC500CD is not a turnkey imaging system, and it does not try to be one. It is a flexible, high-performance acquisition front end. If you are building an imaging research platform, the parts you need are on one card, and you can avoid re-spinning the acquisition board for each new modality.
A practical path: start with the clock tree and the JESD204B fabric, and distribute SYSREF across the carrier from day one. Choose the coupling, trigger use and DAC role for each modality. Bring up the first system on a single module, then add FMC sites as channel count grows, keeping the clock tree and fabric shared throughout. This also connects with the radiation-tolerant direction Sundance DSP is exploring in its work on PolarFire SoC imaging systems.
Mission Possible, in the sense that matters on a bench: what looks like three hardware projects becomes one platform you can build, test and ship.
Which modality are you designing for, and where does your front end hit its limits? I’d like to hear about it in the comments.
References
- Sundance DSP. FMC-ADC500CD product page.
- Texas Instruments. ADS54J60 datasheet.
- Texas Instruments. DAC39J84 datasheet.
- Analog Devices. HMC7044 datasheet.
- Analog Devices. High Performance Data Converters for Medical Imaging Systems.
- Analog Devices. New Digital Demodulator and JESD204B Ultrasound Analog Front End Reduces Data Rates.
- Ultrafast Ultrasound Imaging System With Beamforming on a Single FPGA. arXiv:2208.03429.
- Advantages and Pitfalls in 3T MR Brain Imaging. PMC7976112.
- Magnetic Resonance Imaging, Medical Imaging Systems. NCBI Bookshelf.
- RF Receivers: Signal Detection Chain, Digitization, System Noise Figures. ISMRM 2017.