Two standards, one mezzanine ecosystem The FPGA Mezzanine Card family gives hardware engineers a way to separate the FPGA carrier from the I/O front end. Buy one carrier, swap the mezzanine, and the same processing platform becomes a data acquisition system, an RF...
- Mixing and Matching FMC and FMC+ Boards: A Practical Guide
- Why “Made in the USA” Matters for Critical Aerospace and Defense FPGA Deployment
- Demystifying Algorithmic Trading: Scaling Bollinger Bands from Python to Versal Gen 2 Hardware
- Why the SOM1-SOC (PolarFire SoC) Suits Radiation-Resistant Medical Imaging Systems
- VPX and VNX+: Complementary Siblings, Not Competing Standards
- Unbricking & Reflashing U-Boot and Linux on the SundanceDSP PolarFire SoC (SOM1-SoC and PolarBerry)
- Beyond the Bezel: Solving the FMC Breakout Problem Without Sacrificing Signal Integrity
- Architecting the Secure Edge: A Guide to Learning High-Reliability FPGA SoC Development with PolarFire and PolarBerry
- Overcoming Host Jitter Using Mini PCIe PolarFire FPGAs
- Using the PolarBerry RPI Connector
Mixing and Matching FMC and FMC+ Boards: A Practical Guide
Why “Made in the USA” Matters for Critical Aerospace and Defense FPGA Deployment
“Made in the USA” is sometimes treated as a marketing footnote, a nice-to-have on a datasheet rather than a factor that shapes a procurement decision. In critical aerospace and defense electronics, that view undersells what domestic manufacturing actually...
Demystifying Algorithmic Trading: Scaling Bollinger Bands from Python to Versal Gen 2 Hardware
In high-velocity financial markets, success often depends on two things: a statistical edge that survives real-world frictions, and the speed at which you can act on it. This article walks through a classic quantitative approach, the mean-reversion strategy using...
Why the SOM1-SOC (PolarFire SoC) Suits Radiation-Resistant Medical Imaging Systems
Introduction Medical imaging equipment lives close to radiation. CT scanners, angiography suites, C-arms, linear accelerators, and PET/SPECT scanners all place sensitive electronics near an active radiation source. Sometimes the electronics sit just centimeters away....
VPX and VNX+: Complementary Siblings, Not Competing Standards
Introduction In rugged embedded computing, it’s tempting to treat every new form factor as a replacement for the last one. VNX+ is often described that way, as “the next VPX” or “VPX, but smaller.” That framing misses the point. VPX...
Unbricking & Reflashing U-Boot and Linux on the SundanceDSP PolarFire SoC (SOM1-SoC and PolarBerry)
If you have worked with the Microchip PolarFire SoC architecture, specifically on customized hardware modules like the SundanceDSP SE301 / SOM1-SoC or PolarBerry, you quickly realize that traditional embedded boot mechanics do not apply here. Unlike an ARM chip that...
Beyond the Bezel: Solving the FMC Breakout Problem Without Sacrificing Signal Integrity
FMC-GPIO module: the split-architecture design ships as an FMC module, a matching auxiliary card, and two flex cables. Full product page and STEP files. The Hook: Why Your FMC Breakout Board Is Fighting You Every FPGA engineer who has built a...
Architecting the Secure Edge: A Guide to Learning High-Reliability FPGA SoC Development with PolarFire and PolarBerry
1. Introduction: The High-Stakes Shift to Secure Edge Computing For decades, embedded systems engineering treated security as a software-layer afterthought, a firmware patch, a TLS stack, a password policy bolted onto hardware that was never designed to resist a...
Overcoming Host Jitter Using Mini PCIe PolarFire FPGAs
Achieving Sub-Microsecond (Nanosecond-Class) Multi-Axis Motor Synchronization 1. Introduction: The Multi-Axis Synchronization Problem Multi-axis robotic cells, high-speed CNC gantries, and packaging assembly lines share a common structural dependency. Every...
Using the PolarBerry RPI Connector
Introduction Embedded systems are rapidly evolving beyond traditional centralized computing models. Today’s industrial, defense, communications, and AI applications increasingly require intelligent processing at the edge, where data is generated. These systems...
Versal Gen 2 and SDR Supplementary Part: Enabling Next-Generation Deterministic SDR Systems
SE2000 + FMC-ADC500CD The four-part “Versal Gen 2 and SDR” series is now complete. It covered architectural evolution, decoupling vector math operations, solving data starvation challenges, and the critical path from model to mission in Software Defined Radio (SDR)...
Versal™ Gen 2 and SDR Part 4: Model-to-Mission
Verifying and Deploying Next-Gen Waveforms The final stage of any advanced SDR or DSP system is bridging the gap from algorithmic models to reliable mission deployment, especially in aerospace and defense environments. The AMD Versal Gen 2 AI Edge SoC on the...