FPGA IP Cores

As a member of Xilinx Xpert program Sundance DSP has designed many IP cores for DSP applications in Virtex 2 Pro, Virtex 4 and Virtex-5 FPGAs. Sundance DSP has also designed custom FPGA IP cores for large customers like the US Navy and General Dynamics. The cores include Fixed point FFT, Quadrature Conversion, Advanced Polyphase filter, Power Spectrum, and 64 bit EMIF interface to TI DSPs.

Sundance DSP also provides sophisticated FPGA and DSP Design Automation tools like PARS (Parallel Application from Rapid Simulation) where your entire application could be designed in Simulink from Mathworks and then automatic code, targeting a heterogeneous system comprising multi-DSP and multi-FPGA, be generated automatically. This Rapid Application Development (RAD) tool can help your company\’s products a faster route to the market.

Sundance DSP can help customers with advanced FPGA IP cores for many applications like, Software Defined Radios (SDR), Data Logging, Image processing, MPEG and JPEG compression and many more. Special firmware and IP Cores can also be written for processing of ADC and DAC data on the fly. Please call us to find out how we could help with your DSP and FPGA applications.

FC-1553 Unlimited channels STD1553 core

FC-1553  Unlimited channels STD1553 core
FC-1533 is Mil-Std-1553 IP for FPGAs and ASIC, suitable for any MIL-STD-1553 BC,RT,MT implementation. VHDL code is technology independent.

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FC-A429 Rx & Tx, 429 channels FPGA core

FC-A429  Rx & Tx, 429 channels FPGA core
The FC-A429 macro implements a ARINC 429 protocol with Transmit and Receive Controllers . It allows for the parallel-bus microprocessor communication.

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FC-CANbus Mezzanine Dual or Quad CANbus core

FC-CANbus  Mezzanine Dual or Quad CANbus core
FMC-CANbus IP supports CAN 2.0 & CAN-FD (ISO 11898- 1.2015, plus earlier ISO and Bosch specifications) TTCAN (ISO 11898-4 level 1)

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FC-GPIO VITA57 FPGA Mezzanine I/O module

FC-GPIO  VITA57 FPGA Mezzanine I/O module
The FC-GPIO core has two clock domains. All registers are in system clock domain except RGPIO_IN that can be clocked by system or external clock reference.

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FC118 – Complex FFT FPGA core

FC118  – Complex FFT FPGA core
The FC118 FPGA IP core is a high-resolution complex Fast Fourier Transform

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FC120 – Flexible FPDP protocol

FC120 –  Flexible FPDP protocol
Highly flexible interface for communication using Serial Front-Panel Data Port protocol.

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FC130 – Digital Down Converter

FC130 – Digital Down Converter
Optimized Digital Down Converter Core for Virtex 4 and Virtex 5 Xilinx FPGAs.

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FC200 – Fixed Point FFT FPGA core

FC200 – Fixed Point FFT FPGA core
Fixed Point FFT Processor Core for FPGA. 32 to 1024 points (or more).

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FC201 – General Offset/Gain delay

FC201 – General Offset/Gain delay
Standard Offset/Gain/Delay correction - FPGA IP Core.

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FC202 – Quadrature Conversion

FC202 – Quadrature Conversion
Quadrature Conversion Algorithm - FPGA IP Core.

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FC203A – Power Spectrum Extraction/Exchange core

FC203A – Power Spectrum  Extraction/Exchange core
Power Spectrum Extraction/Exchange of a digital signal.

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FC203B – Power Spectrum Interleave

FC203B – Power Spectrum Interleave
FC203B Power Spectrum Interleave - FPGA IP Core.

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FC205 – Multi-port Serial Transceiver

FC205 – Multi-port Serial Transceiver
Multi-port Serial Transceiver, FC205 provides a user select-able number of standard serial UARTs

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FC300 – 802.11a/g/n OFDM physical layer

FC300 – 802.11a/g/n OFDM physical layer
FC300 is an FPGA IP core implementing the complete OFDM physical layer, based on 802.11a/g/n.

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