Examining the Core Vector Engines The true power of the AMD Versal architecture for Software Defined Radio (SDR) and Digital Signal Processing (DSP) lies not solely in the programmable logic or the processing subsystem, but in the array of specialized vector processors known as AI Engines. While initially marketed toward machine learning inference, SDR and […]
How Versal Gen 2 Elevates Edge SDR Performance In the demanding world of Software Defined Radio (SDR) for aerospace and defense applications, the transition from traditional FPGA-centric designs to heterogeneous adaptive SoCs has been transformative. The AMD Versal Gen 2 AI Edge Series, particularly when integrated into platforms like the SundanceDSP SE2000 3U VPX module […]
If you’re working on embedded systems, networking equipment, video processing, or anything needing tight integration of software and custom hardware acceleration, AMD’s adaptive SoCs are strong contenders. These combine processors, programmable logic, and specialized blocks on one chip. In this post, I’ll compare the Zynq UltraScale+ family with the first-generation Versal Prime and the newer […]
Reno, NV — [May 19, 2026]: SundanceDSP, a leading provider of embedded vision, FPGA acceleration, and rugged edge‑AI platforms, is pleased to announce the release of the FG650-Polarfire, a new variant of the company’s proven FG650 Four‑Channel Camera Link Frame Grabber, now fully implemented on the Microchip PolarFire® FPGA family. The FG650-Polarfire delivers the same […]
Developing OpenVPX and SOSA-aligned systems often requires significant infrastructure before meaningful software, FPGA, or system-level validation can even begin. Engineers frequently depend on full VPX chassis, backplanes, cooling systems, and power subsystems just to start development and debugging. At Sundance DSP, we are focused on simplifying that workflow by providing practical development platforms that reduce […]
After years of battling routing congestion, painful timing closure, and excessive fabric resource usage in large UltraScale+ designs, the hardened Network-on-Chip (NoC) in AMD’s Versal platform stands out as a genuine architectural advancement. Instead of building a complex system interconnect entirely from programmable logic resources, Versal introduces a packet-switched, hardened backbone that serves as the […]
What the ISP in AMD Versal Gen 2 Actually Does (and How It’s Different From Gen 1) If you’ve worked with Versal Gen 1, you already know the deal: there was no hardened ISP on the chip. If you wanted an imaging pipeline, you either built it in the programmable logic, bought an external ISP, […]
When you’re running a Vision LLM on an AMD© Versal™ AI Gen 2, the real magic happens in how the chip moves data around. It’s not just about raw math speed; it’s about making sure the processors aren’t sitting idle waiting for information. The Role of the AIE-ML Gen 2 Tile Think of the AIE-ML Gen 2 tile as […]
Leveraging RFSoC and AI for Non-Cooperative Communication in Harsh Environments Introduction In the domain of signal intelligence (SIGINT), detecting and analyzing communications from non-cooperative senders presents formidable challenges. A non-cooperative sender is characterized by its intent to evade detection, often employing low signal-to-noise ratio (SNR) transmissions, unknown modulation schemes, and bursty, intermittent signaling patterns. These […]
We are thrilled to announce that Sundance will be presenting at the upcoming FPGA Frontrunner 2026 event. Our Chief Innovation Officer, Dr. Mans Ahmadian, will take the stage to unveil our latest work: a defense-grade secure workflow for manufacturing, testing, and programming FPGAs. As defense and aerospace systems evolve, the security perimeter has shifted. Protecting data in the field is […]