DSP802.11S IEEE802.11 a/b/g/- SISO and MIMO Development Platform


The DSP802.11S is a complete SDR development/demonstration system comprising low-cost development hardware, software, and firmware.  FC802.11 is the firmware component of the solution for implementing 802.11 /a/b/g. The software-configurable core is a fully operational implementation of the 802.11 a/b/g (OFDM) basic functionalities including MAC capabilities. The core and software are designed to target GPP/FPGA architectures including Xilinx Zynq FPGA with an embedded ARM processor. The core is very flexible and designed to be adapted within existing advanced Software Digital Radio (SDR) frameworks and application platforms. DSP802.11S is also supported by Sundance DSP SDR400 RF FMC and suitable FPGA boards. Advanced design flows and testing approaches such as HSL (High-Level Synthesis) and Matlab /Simulink are supported.

Different modules of the DSP802.11 form an OFDM PHY (physical interface) which conforms to standard 802.11 specifications. Since being fully configurable, it may be used to implement custom OFDM-based solutions. MAC layer is also available.

Scrambling, Coding, Interleaving, and Mapping are done in the GPP (programmed in C language).

AGC, FFT/DFT, and Autocorrelation real-time and data-intensive operations are performed within the FPGA (or alternatively in GPP).


PHY Layer

  • Protocols a/b/g
  • Transmission OFDM
  • FEC Coding Rates ½, 1/3, 3/4
  • Sub-channel Modulation BPSK, QPSK, 16QAM, 64QAM
  • FFT/DFT (complex) 256 and 512 points
  • PHY Data Rates up to 54 Mb/s
  • OFDM Symbol Duration          4 µsec

 MAC Layer

  • Reduced capability subset for basic Rx/Tx operations
  • TCP/IP proxy capability
  • Data Plane Frame Aggregation
  • Control Plane Enhanced Block Ack. TxBF Control, Protection
  • Management Plane Channel Switching



  • Complete Control and Flexibility, Fully Configurable

Simple and configurable design by configuration flags and values for different modes, number of sub-channels, operating frequencies (from 70 MHz to 6 GHz).

  • Xilinx and Altera FPGAs (in Verilog/VHDL)
  • FPGA control through 32 x 32-bit registers
  • SISO and MIMO configurations
  • Multiple Test Modes

Software, Digital, RF (near & far end loopback). Data Patterns (55, CC, F0), Scrambling. BER evaluation and EVM calculation. Test waveforms, Beacon generation.

  • All 802.11 Transmission Rates up to 54 Mbits
  • Independent Transmit (Tx) and Receive (Rx) chains
  • Non-OS and Linux capabilities
  • Advanced Wireless Sensing

Multi Correlation capability to monitor the spectrum



  • SDR-based WLAN systems (ground, marine, airborne, space)
  • Fixed and mobile AdHoc custom wireless networks 802.11-like
  • wideband wireless communication systems
  • Spectrum sensing and monitoring
  • ELINT/COMINT systems
  • Military wideband communication systems



Block Diagram


DSP802.11D This is a demo system including, hardware, firmware and software for the ARM processor embedded in the Zynq FPGA. All firmware and software are supplied in binary.

DSP802.11S This is a complete system including, hardware,  and all firmware and software supplied in source form for conducting experiments and port to other platforms.