PXIe-720 hardware, a PXIe format FPGA card with an 8-lane PCIe interface and HPC FMC+ daughter card connector





  1. PXIe form factor with 8 lanes of PCIe Gen 3 EP interface to host;
  2. PXI control signals for instrumentation support;
  3. Base FPGA is XCKU060-2FFVA1517E, also can support XCKU085 and XCKU115 version as build option;
  4. SFP+ cage to provide 10Gb Ethernet;
  5. HPC FMC+ connector with 23 FMC_DP 16.3 Gbps serial links, 34 LA, 24 HA and 22 HB lanes;
  6. Supported VADJ – 1.0 – 1.8V;
  7. Two channels of DDR4 SDRAM memory, each 4GB deep and 32-bit wide, base chip is MT40A1G16TB-062E;
  8. 128MB of QSPI flash with multi-boot capability;
  9. Core power up to 50Amps;
  10. Four User LEDs, two of them visible from front panel, power good LEDs, not visible from front panel;
  11. Clock resources to support White Rabbit extreme-precision time protocol via SFP+ fiber.
  12. MMCX internal connectors for:
    • 2 Transceivers from 229 Bank – differential input/output;
    • Reference clock for 229 Bank – differential input;
    • Reference clock for Bank 24 – input SE 1.8V LVCMOS.



More photos coming soon





PXIe720 Front panel      



Block Diagram