Sundance DSP Solar Express 50 (SE50): Adding High-Speed GPIO to a Host System

Most host systems (industrial PCs, embedded controllers, single-board computers) run out of I/O long before they run out of compute. A handful of GPIO pins, a slow parallel bus, no deterministic path for fast signals. The Sundance DSP Solar Express 50 (SE50), a full-size Mini PCIe FPGA module the company calls the “Tiny Beast,” is built to close that gap. It slides into a host’s Mini PCIe slot and, in Sundance’s words, “provides additional processing power, GPIOs as well as high-speed transceivers to the host.”

Here’s how the SE50 adds high-speed GPIO to a host system, and how data captured on those GPIOs gets processed on the FPGA and moved to the main processor by DMA for further processing or display.

What the SE50 is

The SE50 is a small board: 30 mm wide, 50.95 mm long. At its center sits a Microchip PolarFire MPF300T-1FCVG484E FPGA, backed by 4 GB of DDR4 and a PCIe Gen2 x1 interface that runs as a PCIe Endpoint. Sundance calls it “suitable for application processing or for providing additional IO interface to the host” and lists industrial automation, control, and defense as its target markets. The same package also accepts the cheaper MPF100T and MPF200T, so the board comes in three variants (SE50 product page).

Sundance DSP Inc. builds the board in the USA. The company also designs custom FPGA IP cores for DSP, imaging, and defense work (About Us, FPGA IP Cores).

What’s on the board

Device-level FPGA specifications are from Microchip’s MPF300T product page and the PolarFire FPGA Product Overview.

How the SE50 adds high-speed GPIO to a host

It plugs into a slot the host already has

The SE50 is a full-size Mini PCIe card. The Minicard standard defines a 52-pin card edge connector, and the SE50 presents itself to the host as a PCIe Gen2 x1 Endpoint. No custom backplane, no carrier board. The module slides into any Mini PCIe socket (or an mPCIe-to-PCIe adapter), enumerates like any other PCIe device, and becomes a peer of the main processor with its own memory and I/O.

Its GPIO live in the FPGA, not in a fixed expander

The Samtec SS4 high-density connector on the board breaks out general-purpose I/O and high-speed transceiver lanes from the PolarFire fabric. Those pins are FPGA pins, so they carry no fixed function. You define them in hardware. PolarFire I/O supports LVDS and high-speed memory-style standards at up to 1.6 Gbps, and the transceivers reach 12.7 Gbps for serial links. One SE50 can expose many parallel GPIO channels, several custom serial protocols, and high-speed serial links, all to a host that previously had a few slow GPIO pins.

Pin count is a board-design decision. The package supports up to 512 user I/O at the device level, but Sundance does not publish a per-pin map for the SE50, so confirm the breakout with the vendor for a specific design.

A breakout board makes the I/O reachable

Sundance also sells the SE50 Break Out Board (SE50-BO). It puts RF-type connectors on the fast signals, a rectangular IDC connector on the rest, and includes a flexi cable for relocating the module where it’s easier to wire. The board can also connect directly to the SE50 without the cable.

The data path: capture on GPIO, process on the FPGA, DMA to the host

The SE50’s real strength is a pipeline that keeps the host out of the loop until the data is ready. Data gets captured on the GPIOs at fabric clock rates, processed in the FPGA fabric, buffered in the 4 GB DDR4, and transferred to the main processor by DMA over PCIe. The figure below shows where each stage runs.

Stage 1: Capture on the GPIO

Sensors, encoders, ADCs, cameras, and serial links feed signals straight into the FPGA fabric, sampled at the fabric’s clock rate. Dedicated logic can deserialize standard encoder protocols like BiSS-C or EnDat in parallel, or implement a custom framing protocol. No CPU, no driver in the path.

Stage 2: Process on the FPGA

Processing in hardware means filtering, decimation, FFTs, edge detection, and feature extraction run in parallel with deterministic latency. SundanceDSP’s reference architecture for multi-axis motor control closes its control loops largely in the PolarFire fabric because a general-purpose host CPU can’t meet microsecond-level timing determinism (Overcoming Host Jitter Using Mini PCIe PolarFire FPGAs).

Stage 3: Buffer in DDR4

Processed values are written into the 4 GB DDR4 at wire speed, for example as a circular telemetry buffer, with no host software in the write path. Capture is fully decoupled from the host. The board keeps recording while the host is busy, and the buffer doubles as a high-resolution “black box” for fault analysis.

Stage 4: DMA to the main processor over PCIe

When the host needs the data, a DMA engine in the FPGA logic moves completed buffers from DDR4 to host memory in burst transfers over the PCIe Gen2 x1 link. The host CPU never touches the capture loop; it consumes finished frames. Sundance’s design guidance is to give control-plane register writes (setpoint updates from the host, say) priority over diagnostic-plane burst reads, so a large DMA read can’t stall the live processing cycle.

On bandwidth. PCIe Gen2 x1 offers up to roughly 500 MB/s of theoretical per-direction bandwidth, and Sundance notes sustained DMA throughput will be somewhat lower once protocol and transaction overhead are counted. That’s plenty for control setpoints, feature vectors, and decimated telemetry. Raw, un-decimated high-rate streams are a different story, and that’s exactly why the on-FPGA reduction in Stage 2 matters.

Stage 5: Further processing and display on the host

The main processor picks up ready-to-use data through a standard PCIe driver and runs the application layer: more analytics, storage, and the HMI or dashboard that shows results to the operator. The host keeps the supervisory jobs (trajectory planning, non-real-time tasks) while the FPGA owns the fast timing domain.

Choosing a PolarFire variant

The SE50 ships with the MPF300T, but the same package accepts the smaller MPF100T and MPF200T. The real question is how much fabric the application needs once the capture and processing logic is written:

The chart shows how much fabric the three SE50 variants carry. Values are from Microchip’s PolarFire FPGA Product Overview.

Suggested applications

Sundance lists industrial automation, control, and defense as the headline markets. Given the capture-process-DMA pipeline above, the board fits any host that needs many fast I/O channels without loading the main processor:

• Industrial automation and machine control (vendor-listed): high-channel-count sensor and actuator I/O with deterministic timing.
• Multi-axis motion control, CNC, and robotics: Sundance’s reference architecture uses the SE50 to synchronize servo loops in the fabric while the host handles planning and HMI.
• High-speed data logging and telemetry: the DDR4 ring buffer plus the DMA path make a compact always-on recorder for fault post-mortems and commissioning.
• Protocol bridging and conversion: implement BiSS-C, EnDat, or proprietary serial protocols in fabric and hand normalized data to the host over PCIe.
• Machine vision pre-processing: transceiver lanes, 300K logic elements, and 4 GB of buffer suit line-scan or camera-link-style front-end reduction before the host sees frames.
• Test, measurement, and instrumentation: parallel capture channels with timestamping, decimation, and FFT in hardware.
• Defense and avionics (vendor-listed): Sundance’s portfolio includes ARINC 429, CAN, and other avionics-style protocol cores that can be integrated with the SE50’s fabric.

Getting started

The SE50 is programmed over its JTAG headers, and customers can get a free license of Microchip’s Libero SoC toolchain (registration required) for the small device class. One thing to keep straight: as shipped, the SE50 is a general-purpose FPGA carrier. The GPIO capture logic, the on-FPGA processing, and the PCIe DMA engine are custom IP the integrator designs and loads onto the fabric. SundanceDSP helps with stock FPGA IP cores and custom design services. Development happens in Libero SoC, the bitstream lives in the board’s FPGA  Flash, and because PolarFire is flash-based, the board is configured and running within milliseconds of power-up. No external configuration PROM load sequence.

Conclusion

The SE50 is a compact, incremental way to give a host system far more high-speed GPIO than it was built with. The Mini PCIe endpoint drops into an existing slot. The Samtec connector exposes FPGA-backed GPIO and transceivers. And the fabric captures and processes data at hardware speeds before a DMA engine hands finished buffers to the main processor over PCIe. For industrial control, multi-axis motion, or high-rate data logging, the split is the point: fast, deterministic work on the FPGA; supervisory work, display, and further processing on the host. That’s what the Tiny Beast is for.

References

1. Sundance DSP: Solar Express 50 (SE50), “tiny beast”
2. Sundance Technology: Solar Express 50 (SE50)
3. Sundance DSP: Overcoming Host Jitter Using Mini PCIe PolarFire FPGAs (July 15, 2026)
4. Sundance DSP: SE50 Break Out Board
5. Microchip Technology: MPF300T
6. Microchip Technology: PolarFire FPGA Product Overview (DS60001657)
7. Sundance DSP: About Us
8. Sundance DSP: FPGA IP Cores