Developing OpenVPX and SOSA-aligned systems often requires significant infrastructure before meaningful software, FPGA, or system-level validation can even begin. Engineers frequently depend on full VPX chassis, backplanes, cooling systems, and power subsystems just to start development and debugging. At Sundance DSP, we are focused on simplifying that workflow by providing practical development platforms that reduce […]
After years of battling routing congestion, painful timing closure, and excessive fabric resource usage in large UltraScale+ designs, the hardened Network-on-Chip (NoC) in AMD’s Versal platform stands out as a genuine architectural advancement. Instead of building a complex system interconnect entirely from programmable logic resources, Versal introduces a packet-switched, hardened backbone that serves as the […]
What the ISP in AMD Versal Gen 2 Actually Does (and How It’s Different From Gen 1) If you’ve worked with Versal Gen 1, you already know the deal: there was no hardened ISP on the chip. If you wanted an imaging pipeline, you either built it in the programmable logic, bought an external ISP, […]
When you’re running a Vision LLM on an AMD© Versal™ AI Gen 2, the real magic happens in how the chip moves data around. It’s not just about raw math speed; it’s about making sure the processors aren’t sitting idle waiting for information. The Role of the AIE-ML Gen 2 Tile Think of the AIE-ML Gen 2 tile as […]
Leveraging RFSoC and AI for Non-Cooperative Communication in Harsh Environments Introduction In the domain of signal intelligence (SIGINT), detecting and analyzing communications from non-cooperative senders presents formidable challenges. A non-cooperative sender is characterized by its intent to evade detection, often employing low signal-to-noise ratio (SNR) transmissions, unknown modulation schemes, and bursty, intermittent signaling patterns. These […]
We are thrilled to announce that Sundance will be presenting at the upcoming FPGA Frontrunner 2026 event. Our Chief Innovation Officer, Dr. Mans Ahmadian, will take the stage to unveil our latest work: a defense-grade secure workflow for manufacturing, testing, and programming FPGAs. As defense and aerospace systems evolve, the security perimeter has shifted. Protecting data in the field is […]
Model Zoos and Ready-to-Run Models on Vitis AI Introduction to Part 3 Okay, so you’ve got the basics down in parts 1 and 2. Now let’s talk about the model zoo, it’s basically a big collection of ready-to-go AI models that people have already trained and optimized. Instead of building everything from scratch, you grab […]
When you spend enough time around life-dependent systems, one thing becomes obvious: safety isn’t a feature. It’s the foundation. If a music app crashes, it’s annoying. If a medical device fails, someone can die. Same story in a car. At highway speed, you’re trusting software to help steer, brake, deploy airbags, and sometimes even make […]
Machine-vision systems often rely on standardized high-speed interfaces to transfer image data from cameras to processing hardware. Two widely used standards are Camera Link and Camera Link HS. While both are designed for deterministic, low-latency image transport, they differ significantly in architecture, bandwidth, connectors, and implementation platforms. Camera Link: Overview and Key Characteristics Camera Link […]
SundanceDSP is proud to announce that we have completed our first CMMC Level 2 Self-Assessment in accordance with DoD CMMC 2.0 requirements, meeting all applicable Level 2 assessment objectives, with senior official affirmation submitted in SPRS. A major milestone that reinforces our role as a trusted partner for customers across defense, aerospace, industrial, and advanced […]