SE300 is a scalable MIMo solution populated with ADC and DAC FMC+ modules like Sundance DSP FMCP-ADC3p0 and FMCP-DAC12p0. Note that FMCP-DAC12p0 can piggyback an FMCP-ADC3p0 hence the fully populated board will be capable of offering 16 channels of ADC and 16 channels of DAC. It has the capability of capturing/processing data over long distances using the Firefly(c) from Samtec.
SE300 has a PolarFire SoC MPFS460T-FCG1152 as the central unit and 4 Polarfire FPGAs (MPF500T-FCG1152) as FMC+ controllers. Also, there is a flexible clock tree with JESD204B capable of inter-chip synchronization, which allows the creation of coherent systems with 4 FMC+ mezzanine cards.
PolarFire MPSOC is an FPGA + RISC-V processor. PolarFire SOC has a 5-core RISC-V processor (PS part) and programmable Logic (PL) resources.
The board offers the following main interfaces:
- SODIMM 260 pin connector, with a 32-bit interface for the PS part;
- SODIMM 260 pin connector, with a 64-bit interface for the PL part;
- 32MB SPI Serial FLASH for storing boot image;
- 8GByte of eMMC storage for various purposes;
- Two RJ45 with 100/1000BASE-T interfaces;
- USB 2.0 HOST interface, for user purposes;
- Two SFP+ connectors;
- Full or Half-size mPCIe connector with PCIe x1 interface;
- SATA connector, with SATA 3.0 interface;
- 16 XCVRs routed to slave units, 4 XCVR each;
- Star topology low-speed LVDS connections to each unit, 4 pairs to each unit*;
- User LEDs;
- Main Unit – PolarFire SOC FPGA from Microchip (MPFS460T-FCG1152);
- Slave units – PolarFire FPGA MPF500T-FCG1152;
- Flexible clock tree with JESD204B capability, based on HMC7044;
- Inter unit communications with high-speed transceivers;
- Inter unit communications with low speed LVDS mesh connections;
- 4 FMC+ connectors with 16 ten gigabit transceivers, and GPIOs LA[00:33], HA[00:23]* each;
- VADJ is separately regulated for each FMC+ slot;
- JTAG chain with all 5 units;
- USB bridge with JTAG and UART interfaces;
- Power IN – 12V;
- Power consumption of module is 60W (excluding FMC+ mezzanine consumption);
- Data logging MIMO systemDefense and Aerospace
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
- Electronic test and measurement systems
- Phased array radar and electronic warfare
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
A complete Libro project showing the capture of ADC signals by using JESD204B IP core with sample data sent to a host via SFP+ will be provided.
where X can be 1,2 ,3 or 4. Default is 1
T is either E for extended temperature or I for industrial.
All parts will be -1 speed grade
For a bundle price with ADC and/or DAC FMC+ modules please contact SDSP.