The FC-GPIO core has two clock domains. All registers are in system clock domain except RGPIO_IN that can be clocked by system or external clock reference.
Category Archives: IP Cores
FMC-CANbus IP supports CAN 2.0 & CAN-FD (ISO 11898- 1.2015, plus earlier ISO and Bosch specifications) TTCAN (ISO 11898-4 level 1)
The FC-A429 macro implements a ARINC 429 protocol with Transmit and Receive Controllers . It allows for the parallel-bus microprocessor communication.
FC-1533 is Mil-Std-1553 IP for FPGAs and ASIC, suitable for any MIL-STD-1553 BC,RT,MT implementation. VHDL code is technology independent.
FC300 is an FPGA IP core implementing the complete OFDM physical layer, based on 802.11a/g/n.
FC203B Power Spectrum Interleave – FPGA IP Core.
Power Spectrum Extraction/Exchange of a digital signal.
Quadrature Conversion Algorithm – FPGA IP Core.
Standard Offset/Gain/Delay correction – FPGA IP Core.
Fixed Point FFT Processor Core for FPGA. 32 to 1024 points (or more).