If you’re working on embedded systems, networking equipment, video processing, or anything needing tight integration of software and custom hardware acceleration, AMD’s adaptive SoCs are strong contenders. These combine processors, programmable logic, and...
Choosing the Right Adaptive SoC: UltraScale+, Versal Prime, or Versal Prime Gen 2
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SundanceDSP Announces FG650-Polarfire: Four‑Channel Camera Link Frame Grabber for PolarFire® FPGAs
Reno, NV — [May 19, 2026]: SundanceDSP, a leading provider of embedded vision, FPGA acceleration, and rugged edge‑AI platforms, is pleased to announce the release of the FG650-Polarfire, a new variant of the company’s proven FG650 Four‑Channel Camera Link Frame...
Streamlining OpenVPX Development with Flexible VPX-to-PCIe Carrier Solutions
Developing OpenVPX and SOSA-aligned systems often requires significant infrastructure before meaningful software, FPGA, or system-level validation can even begin. Engineers frequently depend on full VPX chassis, backplanes, cooling systems, and power subsystems just...
The Programmable Network-on-Chip in AMD Versal Adaptive SoCs: Lessons from Real Designs
After years of battling routing congestion, painful timing closure, and excessive fabric resource usage in large UltraScale+ designs, the hardened Network-on-Chip (NoC) in AMD’s Versal platform stands out as a genuine architectural advancement. Instead of building a...
Understanding the ISP in AMD Versal Gen 2
What the ISP in AMD Versal Gen 2 Actually Does (and How It’s Different From Gen 1) If you’ve worked with Versal Gen 1, you already know the deal: there was no hardened ISP on the chip. If you wanted an imaging pipeline, you either built it in the programmable logic,...
How the Versal Gen 2 AIE-ML Runs Vision LLMs
When you’re running a Vision LLM on an AMD© Versal™ AI Gen 2, the real magic happens in how the chip moves data around. It’s not just about raw math speed; it’s about making sure the processors aren’t sitting idle waiting for information. The Role...
Blind Signal Detection Using PCIe104-Jet and PCIe-RFSOC
Leveraging RFSoC and AI for Non-Cooperative Communication in Harsh Environments Introduction In the domain of signal intelligence (SIGINT), detecting and analyzing communications from non-cooperative senders presents formidable challenges. A non-cooperative sender is...
Securing the Silicon Supply Chain
We are thrilled to announce that Sundance will be presenting at the upcoming FPGA Frontrunner 2026 event. Our Chief Innovation Officer, Dr. Mans Ahmadian, will take the stage to unveil our latest work: a defense-grade secure workflow for manufacturing, testing, and...
Understanding Artificial Intelligence Part 3
Model Zoos and Ready-to-Run Models on Vitis AI Introduction to Part 3 Okay, so you’ve got the basics down in parts 1 and 2. Now let’s talk about the model zoo, it’s basically a big collection of ready-to-go AI models that people have already trained...
SIL3 and ASIL D Explained: What Functional Safety Really Means for AI Systems
When you spend enough time around life-dependent systems, one thing becomes obvious: safety isn’t a feature. It’s the foundation. If a music app crashes, it’s annoying. If a medical device fails, someone can die. Same story in a car. At highway speed, you’re trusting...