PCIe104-RFSOC for Medical Imaging: Where an RFSoC Fits

A medical imaging front end has to digitize many channels and keep them aligned in time. Then it has to move the samples on for reconstruction, inside tight limits on power, board area and cabling. The PCIe104-RFSOC puts an AMD Zynq UltraScale+ RFSoC on a PCIe/104 card. Inside that one device, the data converters sit next to the FPGA fabric and the Arm processors.

This post maps the card onto ultrasound, PET and MRI. It also covers where the card does not fit, because in some places a dedicated ultrasound chip or a remote MRI head is the better tool.

The challenge in numbers

Ultrasound is about channel count and data rate, while PET and MRI stress other parts of the chain. A Medical Design and Outsourcing article by Analog Devices engineers calls 128 channels the mainstream setup, and premium systems are moving to 192 or more. The authors’ worked example uses 14-bit ADCs at 40 MSPS. That gives 71.68 Gbps of raw data for 128 channels, before any processing.

But demodulation changes the picture. Each channel can move to I/Q baseband and decimate to a 3.5 MHz output rate, with 16-bit I and Q samples. After that step, the same 128 channels need 14.336 Gbps, which is 80% less. The article also counts the wiring: 160 LVDS pairs for 128 channels, against 32 JESD204B lanes.

Figure 1: Ultrasound data rate before and after demodulation. The figures come from the Medical Design and Outsourcing example for 128 channels. Demodulating early cuts the rate the back end has to carry by 80%.

PET puts the stress on event rate and timing instead. The OpenPET detector board paper targets systems with more than 1,000 channels and over one million events per second.

Its 16-channel board reads pulse height with a 12-bit ADS5282 ADC that runs at 10 to 65 MSPS. A time-to-digital converter (TDC) in the FPGA firmware then stamps each event. With test pulses, the authors measured about 90 ps FWHM.

MRI is a timing and noise problem. Skope’s lean RF head digitizes 16 channels next to the scanner and sends the data out over fiber. Skope notes that other groups have built 128-channel receivers. Its own head syncs to an external trigger to better than +-10 ns.

Why an RFSoC fits

In a discrete design, an external ADC talks to the FPGA over a serial link such as JESD204B. Then the fabric filters and decimates the stream. Each of those steps costs pins, layout effort and power. An RFSoC instead puts the RF-ADCs and RF-DACs, with their digital down-converters (DDC) and up-converters (DUC), on the same die as the FPGA fabric.

AMD says this integration removes the need for external data converters. It claims up to 50% less power and footprint than a multi-component design. It also drops FPGA-to-analog interfaces like JESD204. Treat the 50% as AMD’s best case against a discrete baseline, not a number for your system.

The engineering point still holds, because the converter, the decimation and the fabric become one part. What you still own is the analog conditioning in front of the connector and the clock plan.

The PCIe104-RFSOC front end

The default device on the card is the AMD XCZU47DR. The ordering code lists 25DR, 27DR, 28DR, 47DR and 48DR builds, and you can choose -E or -I temperature grades. Since the XCZU47DR is a Gen 3 RFSoC, its converters set the baseline. According to the AMD RFSoC selection guide (XMP105), that gives you:

8 RF-ADCs at 14 bits, up to 5.0 GSPS, each with a DDC.
8 RF-DACs at 14 bits, up to 9.85 GSPS, each with a DUC (AMD lists operation up to 10 GSPS through its sales team).
DDC decimation from 1x up to 40x.

The 25DR, 27DR and 28DR are Gen 1 parts. On those builds the RF-ADCs are 12-bit at up to 4.096 GSPS. The RF-DACs stay at 14 bits but top out at 6.554 GSPS. AMD’s Gen 2 part, the ZU39DR, is not in the card’s ordering code.

One caution before you size a design. The product page names the XCZU47DR as default but quotes the Gen 1 converter rates, with a note that later-generation devices run faster. Its feature list also names the XCZU27DR instead. Confirm the exact device and rates with Sundance for the build you order.

Memory, PCIe and the data path

The RF side uses a Nicomatic connector with up to 8 ADC inputs and 8 DAC outputs, and Sundance supplies the mating cable. The ADC inputs are differential, with AC or DC coupling as a build option. Because of that, you can design whatever input network your sensor needs on your own RF IO board. The DAC outputs are single-ended, 50 Ohm and AC coupled through baluns.

Behind the converters, the PL (the FPGA fabric) has 8 GB of DDR4 with ECC. The PS (the Arm processing system) has its own 8 GB of ECC DDR4. It also has eMMC for boot and the OS. The product page gives two different eMMC sizes, so treat capacity as a build option to confirm.

The main stream leaves through an x8 Gen 3 PCIe root complex driven from the PL. Separately, the PS drives a single PCIe x1 lane to Bank 1 of the PCIe/104 connector. Both are root complexes, which makes the card the host of its stack. It is not an endpoint that plugs into a PC, so plan the route to your reconstruction computer early.

Figure 2: Data path on the PCIe104-RFSOC. The RF-ADCs and DDCs feed the PL fabric. The x8 Gen 3 PCIe link leaves from the PL. Meanwhile, the PS has its own memory and a separate x1 lane to Bank 1.

Ultrasound

Ultrasound is where the card is the weakest fit. One card has 8 RF-ADC channels, so a 128-element head would need 16 cards and a 192-element head 24.

A purpose-built octal ultrasound chip such as the AD9671 covers eight channels in one part. It holds the LNA, VGA, anti-aliasing filter, 14-bit ADC and a digital demodulator. For a production 128-channel scanner, that kind of chip is still the natural choice.

The sample rate tells the same story. The worked example above samples at 40 MSPS, while a Gen 3 RF-ADC runs up to 5.0 GSPS, 125 times faster. At the full 5.0 GSPS, even the maximum 40x decimation leaves 125 MSPS per channel. You pay for converter bandwidth that the decimator then throws away.

The card earns its place elsewhere. It suits research rigs and prototypes, where you want full control of the digital chain in your own firmware. It also suits a small set of channels sampled at high rates. Transmit experiments can use the 14-bit RF-DACs to synthesize custom excitation waveforms.

If you would rather build on FMC, our FMC-ADC500CD medical imaging article walks the same three modalities.

PET

PET front ends read pulse height with an ADC and stamp the leading edge with a TDC. In OpenPET, the TDC lives in FPGA firmware, and a separate Support Board pairs singles into coincidence event words. That split matters here: on the PCIe104-RFSOC, any TDC would also sit in the PL fabric, not in the RF-ADC.

The rates do not favor the RF-ADCs for full detector readout. OpenPET’s board samples at 40 MSPS on 16 channels and targets more than 1,000 channels. For OpenPET-style pulse-height readout, a GSPS converter is far beyond what is needed, since that ADC tops out at 65 MSPS and a separate TDC in the FPGA handles timing. At 8 channels per card, the cost and power per channel also climb fast.

Instead, the card fits best on the processing side. The PL fabric is a reasonable home for timing firmware and coincidence logic. Meanwhile, the PS can format event streams for the rest of the system. Imaging suites also put electronics close to radiation, and our article on why the SOM1-SOC (PolarFire SoC) suits radiation-resistant medical imaging systems covers that side.

MRI

MRI is the modality where direct RF sampling and an on-die DDC map most closely to the job. Each receive channel needs mixing to baseband and decimation. The RFSoC does both right after it digitizes the signal, on the same die.

Placement is the catch. Skope keeps a compact 16-channel head next to the scanner and ships the samples over fiber. Its FPGA and main processing sit in a technical room outside the Faraday cage. An 80 W PCIe/104 stack is not a compact, low-power magnet-side head, so keep this card outside the magnet room.

That leaves two sensible roles. First, your design may bring analog RF out of the magnet room. Then the card can act as an out-of-bore receiver: the RF-ADC samples directly, and the DDC mixes each channel to baseband. Second, you may digitize at the magnet instead, and then the card belongs in the back end.

In that case, a serial link from a remote head could land on the eight GTY transceivers at the LSHM connector. They are absent on the 25DR build. Either way, that link is firmware and hardware you would design and verify yourself.

Figure 3: Where the card fits in each modality. Each arrow names the role this article proposes for the card in that modality. None of them replaces the usual front end for that modality.

Clocking and synchronization

Clocking decides whether a multi-channel front end holds together. On this card, the HMC7044 is the main clocking IC, and it can lock to a user reference clock. LMX2594 parts then clock the ADCs and DACs. The board carries its own clocks by default.

The RF IO connector also takes four optional inputs. They are a PPS GPS signal, an external 10 MHz clock, a reference clock and a Trigger In. For MRI, those inputs are how you tie acquisition to the scanner’s reference and trigger. Skope reached better than +-10 ns against an asynchronous trigger using JESD204B subclass 1 synchronization.

However, the product page does not list a trigger-to-sample timing figure for this card. Measure it on your own build, with your own firmware, before you commit to a timing budget.

Integration: stack-down, temperature, power

The PCIe104-RFSOC is a PCIe/104 Type 1 host board with stack-down connections only. PC/104-family boards stack on each other rather than plugging into a backplane. As the host, this card sits at the top, with expansion cards stacked below it.

The product page gives an operating range of -40 C to +85 C. It does not tie that range to the -E or -I grade, so check it for your build. The page also estimates maximum board power at about 80 W. Plan the thermal path and supply for that before you choose an enclosure.

For I/O, two Samtec LSHM connectors bring out extra PS and PL signals and transceivers. You also get a 100/1000Base-T header, a SATA Gen 3 connector and a USB 3.0 host header. USB-JTAG/UART runs through an FT4232HQ bridge. An INA226 monitors FPGA supply current and voltage.

The board is made in the USA, which matters for some programs. Our post on why Made in the USA matters for critical FPGA deployment explains why. If you need converter density on an FMC+ carrier instead, see four DACs and four ADCs on one FMC+ site. The ordering code is PCIe104-RFSOC-xxDR-T-S, where xx is the device, T the temperature grade and S the speed grade.

Where it fits

The PCIe104-RFSOC gives you eight direct RF-sampling ADCs and eight DACs with on-die down- and up-conversion. Around them sit a large FPGA fabric, 16 GB of ECC DDR4 and a clock tree that can lock to your reference. On a Gen 3 build, the RF-ADCs reach 5.0 GSPS and the RF-DACs 9.85 GSPS.

It is not a drop-in replacement for octal ultrasound AFEs or PET detector boards. That is because the channel count per card is low, and the converters are far faster than those signals need. Instead, it fits MRI receive outside the bore, research or prototype front ends, and the processing and timing side of a larger system. Matching the card to that part of the problem is what turns a crowded front end into a Mission Possible.

Before you order, talk to Sundance about the device, speed grade and eMMC options. The full product page has the complete specification.