SE2000 + FMC-ADC500CD The four-part “Versal Gen 2 and SDR” series is now complete. It covered architectural evolution, decoupling vector math operations, solving data starvation challenges, and the critical path from model to mission in Software Defined Radio (SDR)...
- PolarBerry: A PoE-Powered RISC-V Platform Built for Unattended Ground Sensors
- FMC-CLV: the Camera Link bridge you need when the next generation of FPGAs won’t talk to your old camera
- Mixing and Matching FMC and FMC+ Boards: A Practical Guide
- Why “Made in the USA” Matters for Critical Aerospace and Defense FPGA Deployment
- Demystifying Algorithmic Trading: Scaling Bollinger Bands from Python to Versal Gen 2 Hardware
- Why the SOM1-SOC (PolarFire SoC) Suits Radiation-Resistant Medical Imaging Systems
- VPX and VNX+: Complementary Siblings, Not Competing Standards
- Unbricking & Reflashing U-Boot and Linux on the SundanceDSP PolarFire SoC (SOM1-SoC and PolarBerry)
- Beyond the Bezel: Solving the FMC Breakout Problem Without Sacrificing Signal Integrity
- Architecting the Secure Edge: A Guide to Learning High-Reliability FPGA SoC Development with PolarFire and PolarBerry
Versal Gen 2 and SDR Supplementary Part: Enabling Next-Generation Deterministic SDR Systems
Versal™ Gen 2 and SDR Part 4: Model-to-Mission
Verifying and Deploying Next-Gen Waveforms The final stage of any advanced SDR or DSP system is bridging the gap from algorithmic models to reliable mission deployment, especially in aerospace and defense environments. The AMD Versal Gen 2 AI Edge SoC on the...
Versal™ Gen 2 and SDR Part 3: Solving Data Starvation
Enhanced NoC and the Distributed Memory Matrix In high-performance SDR and DSP systems, raw vector compute capability is necessary but insufficient. Sustained performance is overwhelmingly gated by memory bandwidth, on-chip data movement, and the ability to keep...
Versal™ Gen 2 and SDR Part 2: Decoupling Vector Math
Examining the Core Vector Engines The true power of the AMD Versal architecture for Software Defined Radio (SDR) and Digital Signal Processing (DSP) lies not solely in the programmable logic or the processing subsystem, but in the array of specialized vector...
Versal™ Gen 2 and SDR Part 1: Architectural Evolution
How Versal Gen 2 Elevates Edge SDR Performance In the demanding world of Software Defined Radio (SDR) for aerospace and defense applications, the transition from traditional FPGA-centric designs to heterogeneous adaptive SoCs has been transformative. The AMD Versal...
Choosing the Right Adaptive SoC: UltraScale+, Versal Prime, or Versal Prime Gen 2
If you’re working on embedded systems, networking equipment, video processing, or anything needing tight integration of software and custom hardware acceleration, AMD’s adaptive SoCs are strong contenders. These combine processors, programmable logic, and...
SundanceDSP Announces FG650-Polarfire: Four‑Channel Camera Link Frame Grabber for PolarFire® FPGAs
Reno, NV — [May 19, 2026]: SundanceDSP, a leading provider of embedded vision, FPGA acceleration, and rugged edge‑AI platforms, is pleased to announce the release of the FG650-Polarfire, a new variant of the company’s proven FG650 Four‑Channel Camera Link Frame...
Streamlining OpenVPX Development with Flexible VPX-to-PCIe Carrier Solutions
Developing OpenVPX and SOSA-aligned systems often requires significant infrastructure before meaningful software, FPGA, or system-level validation can even begin. Engineers frequently depend on full VPX chassis, backplanes, cooling systems, and power subsystems just...
The Programmable Network-on-Chip in AMD Versal Adaptive SoCs: Lessons from Real Designs
After years of battling routing congestion, painful timing closure, and excessive fabric resource usage in large UltraScale+ designs, the hardened Network-on-Chip (NoC) in AMD’s Versal platform stands out as a genuine architectural advancement. Instead of building a...
Understanding the ISP in AMD Versal Gen 2
What the ISP in AMD Versal Gen 2 Actually Does (and How It’s Different From Gen 1) If you’ve worked with Versal Gen 1, you already know the deal: there was no hardened ISP on the chip. If you wanted an imaging pipeline, you either built it in the programmable logic,...
How the Versal Gen 2 AIE-ML Runs Vision LLMs
When you’re running a Vision LLM on an AMD© Versal™ AI Gen 2, the real magic happens in how the chip moves data around. It’s not just about raw math speed; it’s about making sure the processors aren’t sitting idle waiting for information. The Role...
Blind Signal Detection Using PCIe104-Jet and PCIe-RFSOC
Leveraging RFSoC and AI for Non-Cooperative Communication in Harsh Environments Introduction In the domain of signal intelligence (SIGINT), detecting and analyzing communications from non-cooperative senders presents formidable challenges. A non-cooperative sender is...